FPGA Implementation Of Efficient Modified VLSI Architecture For Multiplier
D.Vinoth, R.Vinoth, R.Srinivasan, M.M.Arun Prasath , D.Vimala
Abstract
The multiplication operation is present in many parts of a digital system or digital computer and also in signal processing, graphics and scientific computation. With advances in various technologies, various techniques have been proposed to design multipliers, with high speed, low power consumption and lesser area. Various high speed low power compact VLSI implementations are possible only with multipliers. This project presents a high- speed and low area 16×16 bit Modified Booth Multiplier (MBM) with Carry Select Adder (CSA) and 3-stage pipelining technique. These techniques to improve the performance by reducing the time delay. These multiplication techniques are design using hardware description language (HDL) and it can simulate using modelsim software and also it will implement in Spartan 3E FPGA and also power consumption will estimate using tanner EDA tool.
References
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